AI testing: going beyond DFT architectures

The size of massive, highly parallel AI processor chips has a significant impact on design and testing methodologies.

Every day, more and more applications are deploying an artificial intelligence (AI) system to increase automation beyond traditional systems. The continued growth in computing demands for AI systems is forcing designers to develop massive, highly parallel AI processor chips. Their large sizes and types of applications have a significant impact on their design and testing methodologies. With thousands of repeating cores, as well as IP integrated into a system on a chip (SoC), new architectures and design-for-test (DFT) methodologies are needed to maximize the quality of silicon tests while minimizing the costs of testing. test. In addition, AI chips used in safety critical applications, such as autonomous driving, require the highest quality manufacturing testing to achieve less than one defective part per million (DPPM) and need DFT structures to ensure the correct and safe operation of the chips. during system operation. However, adding such DFT logic to the design further increases the size of already large chips.

Leveraging a hierarchical testing methodology is ideal for AI designs. It uses a divide and conquer approach by breaking the design into smaller hierarchical partitions for DFT approval, which includes the following: DFT insertion, test mode setup, model generation, and verification. An AI design can contain multiple levels of hierarchy, each with repeated DFT partitions, and each partition can be a single core or a group of cores depending on the DFT architecture, as shown in Figure 1. With a methodology Hierarchical testing, the DFT trust for each unique partition at a hierarchical level is performed once and reused in all replicated instances. The exact process is repeated at each hierarchical level to gain DFT approval for the entire design, as shown in Figure 2. After completing the DFT at the partition level, configuration and test mode patterns corresponding are carried to the chip level to activate application with automatic test equipment (ATE).


Fig. 1: Typical AI chip showing DFT partitions at different hierarchical levels.


Fig. 2: Hierarchical testing allows DFT disconnection and reuse of partitions at each hierarchical level.

One of the most notable benefits of this methodology is significantly increased productivity and reduced compute resource requirements. This is because the DFT approval task for each unique partition can be performed independently and in parallel with other partitions, using much smaller computing machines than needed for the flat DFT approval methodology, as shown. figure 3.


Fig. 3: Increased productivity and reduced compute resources thanks to a hierarchical test methodology.

In general, AI testing requirements often conflict with stringent power, performance, and area (PPA) requirements. With discrete test streams, DFT logic is generated and added to the design logic without considering its impact on the physical design (PD), and the DFT logic is analyzed in the same way as any other functional logic for the implemented during the PD process. This lack of consideration of DFT logic in the technology for implementing the physical design often results in a degraded PPA for the entire design (user more logical DFT) or a significant delay in the realization of the design. convergence of design. In some cases, a modification of the DFT architecture is necessary to resolve these problems. The degradation becomes more pronounced in the case of AI designs, as a suboptimal DFT logic implementation in one core, made worse when replicated across thousands of cores, has a severe impact on the overall PPA. of the chip.


Fig. 4: Obsolete and discrete test flow with isolated DFT and physical design process.

For these large and complex AI chips, it is easy to understand that just as the DFT architecture and methodologies are important to achieving test goals, a DFT implementation that is physically aware is crucial to minimizing the load on the effort. physical design to achieve optimal PPA. . Therefore, AI chip designers must simultaneously deploy test technology that addresses the combined challenges of optimal DFT architecture and optimal implementation.

Effective and efficient test solutions must optimize the physical implementation of DFT logic to take full advantage of appropriate test methodologies and architectures for AI designs. In addition to supporting hierarchical testing, advanced DFT technologies unify DFT and physical implementation engines into a single, transparent flow for physically-aware DFT design and implementation. Some of the important techniques used by these test solutions include:

Targeted logical and physical optimizations of DFT logic such as automatic distribution of test compression block for placement, intelligent routing of DFT logic, reclassification of test compression connections, clock network optimizations, etc. .


Fig. 5: High sweep compression with congestion optimization (heat map).

Geolocated test points for improved routing and reduced number of models.


Fig. 6: Traditional test points vs. location sensitive test points.

Order based on the location of elements in the scan chain to reduce congestion.


Fig. 7: Congestion with sutured scan cells without and with physical information.

Physically conscious casing cells based on the location of the center pins when inserting the isolation casing.

As the test goals for high-quality, low-cost testing of AI chips become increasingly difficult, test solutions must include a physically aware DFT implementation to enable ideal architectures, time-saving methodologies time and optimal PPA. The application of discrete DFT technologies and flows detached from the current implementation technology invites below average results or a huge effort to compensate. Advanced test technologies that address the challenges of DFT and physical implementation as a unified goal are needed to meet the growing expectations of today’s design and test teams.

Rahul singhal

(All posts)

Rahul Singhal is Product Marketing Manager in the Hardware Analytics & Test group at Synopsys.


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